1. Field of the Invention
The present invention generally relates to a method for forming an electronic device such as a field-effect transistor (FET) device. Specifically, the present invention relates to a method for forming an electronic device in which gate length variation is reduced.
2. Related Art
In the process of manufacturing electronic devices such as FET devices, several factors can lead to gate length variation. One such factor is the incapability of the lithographic tools to produce straight edge gate lines. Another factor is the etching process whereby uneven gate lines are produced. However, a prevailing cause of gate length variation is the grain structure of polycrystalline silicon. Specifically, in the manufacture of many electronic devices such as FET devices, the gate polysilicon is deposited as polycrystalline silicon. The grain-like structure of the polysilicon typically causes gate line roughness during polysilicon etching. In addition, during high temperature processing of the device such as during rapid thermal anneal (RTA) gate sidewall oxidation, the gate polysilicon line roughness is increased as the polysilicon material undergoes further changes in crystal structure in an unconfined environment.
This gate line problem is partly alleviated through the use of amorphous silicon for the gate silicon. Specifically, through the use of amorphous silicon, the increase in the roughness of the gate line is minimized during the gate silicon etch. However, in the conventional use of the amorphous silicon, high temperature processing such as the RTA gate sidewall oxidation and/or high temperature low pressure (LP) chemical vapor deposition (LPCVD) of nitride immediately follows. Exposure of the amorphous silicon to high temperatures causes structural transformation, which when occurring in an unconfined environment, cause movement of the silicon material during the polysilicon grain growth. Thus, the roughness of the gate silicon line is increased, which leads to variation in the gate length. Referring to FIG. 1, a scanning electron micrograph (SEM) image 10 of a polysilicon gate line 12 as produced under the prior art is depicted. As shown, the surface of the polysilicon gate line 12 is rough, which causes variation in the gate length 14. For example, at point 16 gate length 14 is approximately 115 nm. Conversely, at point 18, gate length 14 is approximately 128 nm. Such a variation in gate length 14 can raise significant performance issues in the device.
In view of the foregoing, there exists a need for a method for manufacturing an electronic device. Specifically, a need exists for a method of manufacturing an electronic device in which gate length variation is reduced. A further need exists for a method of manufacturing an electronic device in which amorphous silicon is used as the gate silicon. However, another need exists for the amorphous silicon to be exposed to high temperatures for transformation to polysilicon only in a confined environment.